
`include "defines.v"

module mux_w_data (
    input  wire              rst,
    
    input  wire [`BUS_WIDTH] result,
    input  wire [`BUS_WIDTH] data_out,
    input  wire              mem2reg,

    output reg  [`BUS_WIDTH] w_data
);
    

    
    always @(*) begin
        if (rst) begin
            w_data = `ZERO_WORD;
        end
        else begin
            case (mem2reg)
                1'b0: begin
                    w_data = result;
                end
                1'b1: begin
                    w_data = data_out;
                end
            endcase
        end
    end


endmodule
